1. Field of the Invention
This invention relates generally to solid state components, and more particularly, to a molded chip carrier package that is adapted for mounting on a circuit board. The invention is also directed to the method for making this molded chip carrier.
2. Prior Art
The advent of solid state components, and more particularly the integrated circuit (IC), an electronic device that utilizes a chip of specialized material to perform specific electronic functions, have revlutionized the electronics industry and have practically affected every phase of life today, from consumer goods to computer and business equipment, to military equipment. Amazingly, a small piece of specially prepared material, commonly called a "chip", has replaced antiquated, power consuming, vacuum tubes that were previously used to perform similar electionics functions. Not only has the chip produced similar results, but it has created an entirely new field of electronic capabilites. The chip and its packaging have not only greatly reduced the power consumption in a circuit, but has tremendously decreased the size of the components used in the circuit.
A chip used in an integrated circuit is usually a single substrate on which active or passive circuit elements have been fabricated using one of many well known semiconductor techniques such as diffusion, passivation, masking, photoresist and epitaxial growth. However, a chip is not ready for use until it is packaged within a protective housing which provides external input and output terminals. In the past, most chips have been packaged in rectangular shaped plastic housings that have rows of leads or pins that extend outward from the bottom of the housing. The pins are usually arranged in two parallel rows extending along the length of the housing with each pin positioned near the peripheral edge of the housing. The pins are usually mounted to a circuit board by first placing the pins through pre-drilled holes located in the circuit board and then soldering the ends of the pins to the opposite side of the circuit board. This type of component, generally referred to as a dual-in-line package (DIP), has been the industry standard for a number of years.
Despite the popularity of dual-in-line packages, electronic circuit designers have been seeking alternative packaging to negate some of the problems associated with DIPs. For example, design engineers have found that DIPs which accommodate 64 or more pins consume valuable space on circuit boards; and that as the number of pins increases, the electrical performance of the component decreases. It is quite possible for DIPs having 64 pins or more to have pin lengths up to 1.6 inches as measured from the central chip to the outermost edge of the pin. This length can produce unwanted inductances along with propagation delays to the associated circuitry. Additionally, DIPs require the circuit board to be pre-drilled with properly spaced holes to receive the pins of the DIP. These and other disadvantages prompted many electronic designers to look for new packaging to accommodate the chip.
This search for a smaller and more reliable package prompted the discovery of surface mounted devices (SMD) that are generally mounted and soldered onto one side of a printed circuit board. In order to accomplish this type of mounting, the circuit board has to be printed with conductive pads or "footprints" that correspond to the spacing of the leads on the SMD. The surface mounted device is simply placed on its pads and soldered to the board.
One popular SMD, referred to in the industry as a chip carrier, includes a square or rectangular housing having a central portion upon which the chip or chips are mounted. The chip carrier also includes input and output pins or leads located on all four sides of the housing. Typically, the spacing between the input/output leads is 0.05 inch, half of DIP pin spacing. Additionally, the newer chip carrier packages can take up less than one-fourth of the area that conventional DIPs take up. Also, since the chip carrier has a smaller input/output lead, electrical performance is enhanced through lower inductances and shorter propagation delays.
Chip carriers generally come in two types namely ceramic and plastic. Ceramic chip carries, as the phrase implies, are made from ceramic materials and are generally used for military and other high reliability applications which require ceramics hermeticity and high temperature properties. A ceramic chip carrier is usually leadless, that is, it lacks leads extending on the sides of the carrier body, but rather has small conductive pads located on the bottom surface of the carrier body. Due to their higher quality, ceramic chip carriers are generally more expensive than plastic chip carriers.
Plastic chip carriers, to which the present invention is directed, are more widely used in commercial and industrial applications where the environment is less severe and the need for cost effectiveness dominates. One popular plastic chip carrier includes a plastic-like housing or body which carries a stamped metal lead frame. The lead frame forms numerous individual leads that are bent down around the perimeter of the housing. The leads can be formed under the housing in a shape similar to the capital letter "J". This type of lead, commonly called a J-lead, provides sufficient contact for attaching the chip carrier to a circuit board or other substrate since the J-lead can be soldered to corresponding conductive pads located on the circuit board. Other variations of leads include the gull-wing leads which extend out away from the bottom of the carrier body rather than under it.
While plastic chip carriers are advantageous in some respects over DIPs, they still possess disadvantages which have hindered their acceptance by the industry. One of the main problems encountered has been in the formation of the lead frames that are attached to the carrier body. Since many chip carriers can have as many as 320 leads, precision of shapes and dimensions required in the dies forming the lead frames increase dramatically, which only adds to the complexity and cost of forming a functional component.
Other shortcomings of chip carriers arise during the soldering of the carrier to the printed circuit board. One of the major difficulties encountered in both manufacturing and mounting the chip carrier is in maintaining lead coplanarity (the straightness of each lead with the mounting plane during soldering). Many manufacturers specify that their components must have a coplanarity of .+-.2 to .+-.5 mils in order to achieve proper soldering of the carrier to the circuit board. However, during the manufacturing, transporting and handling of the chip carrier, it is possible for some of the leads to become bent. When this occurs, a technician must rebend the bent leads to enable the chip carrier to properly engage all its mounting pads. If the leads become bent, a technician will have to take additional time and effort to straighten the leads. Sometimes, it is impossible for the technician to properly bend the leads back into their precise shape. When this occurs, the chip carrier becomes useless.
Another shortcoming in using a lead frame is the fact that the leads cannot be bent into elaborate shapes due to the close spacing and thinness of the leads. This effectively reduces the various ways that the leads can be shaped on the carrier body since breakage is possible due to excessive bending. Also, excessive bending can cause some of the leads to come in contact with other leads, which is undesirable in any electronic component. These occurrences can also result in a defective chip carrier.
While the chip carrier has greatly reduced the amount of area that is taken up on a circuit board, it has several disadvantages which hinder its use by some electrical circuit designers. As a result, the electronics industry has not yet fully developed the chip carrier to its full potential as an effective electronic component. Therefore, there is a need for a chip carrier that can be manufactured rather inexpensively and which eliminates these and other disadvantages associated with prior art chip carriers.